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gm71vs65163al 4,196,304 words x 16 bit cmos dynamic ram description features * 4,196,304 words x 16 bit * extended data out (edo) mode capability * fast access time & cycle time *power dissipation - active : 720mw/648mw(max) - standby : 1.8 mw ( cmos level : max ) 0.54mw ( l-version : max) *edo page mode capability *access time : 50ns/60ns (max) *refresh cycles - ras only refresh 4096 cycles/64 a (GM71V65163A) 4096 cycles/128 a (gm71vs65163al)(l_version) *cbr & hidden refresh 4096 cycles/64 a (GM71V65163A) 4096 cycles/128 a (gm71vs65163al)( l-version ) *4 variations of refresh -ras-only refresh -cas-before-ras refresh -hidden refresh -self refresh (l-version) *single power supply of 3.3v+/-10 % with a built-in vbb generator *battery back up operation ( l-version ) (unit: ns) pin configuration the gm71v(s)65163a/al is the new generation dynamic ram organized 4,196,304 words by 16 bits. the gm71v(s)65163a/al utilizes advanced cmos silicon gate process technology as well as advanced circuit techniques for wide operating margins, both internally and to the system user. system oriented features include single power supply of 3.3v+/-10% tolerance, direct interfacing capability with high performance logic families such as schottky ttl. the gm71v(s)65163a/al offers extended data out(edo) mode as a high speed access mode. 50 soj / tsop 1 lg semicon co.,ltd. gm71v(s)65163a/al-5 gm71v(s)65163a/al-6 t rac t aa t rc t hpc 50 60 25 30 90 110 20 25 13 15 t cac (top view) 1 vcc 2 io0 3 io1 io2 4 5 io3 6 7 12 vcc 13 /we vcc io4 11 nc 10 io7 9 io6 8 io5 14 /ras 15 nc 16 nc nc 17 18 nc 19 20 25 vcc a0 a1 24 a5 23 a4 22 a3 21 a2 50 vss 49 io15 48 io14 io13 47 46 io12 45 44 39 vss 38 /lcas vss io11 40 nc 41 io8 42 io9 43 io10 37 /ucas 36 /oe 35 nc nc 34 33 nc 32 31 26 vss a11 a10 27 a6 28 a7 29 a8 30 a9 GM71V65163A
pin description pin function pin function a0-a11 a0-a11 ras ucas,lcas we v cc v ss nc address inputs refresh address inputs row address strobe column address strobe write enable power (+3.3v) ground no connection absolute maximum ratings* symbol parameter rating unit t stg v t v cc i out -55 to 125 -0.5 to v cc + 0.5 (max ; 4.6v) -0.5 to 4.6 50 storage temperature (plastic) voltage on any pin relative to v ss voltage on v cc relative to v ss short circuit output current c v v ma p t 1.0 power dissipation w *note : operation at or above absolute maximum ratings can adversely affect device reliability. recommended dc operating conditions (t a = 0 ~ 70c) symbol parameter unit v cc v ih v il supply voltage input high voltage input low voltage v v v max 3.6 vcc+0.3 0.8 typ 3.3 - - min 3.0 2.0 -0.3 oe output enable i/o0 - i/o15 data input / output 2 lg semicon ordering information type no. access time package gm71v(s)65163a/alj-5 gm71v(s)65163a/alj-6 50 ? 60 ? 400 mil 50 pin plastic soj gm71v(s)65163a/alt-5 gm71v(s)65163a/alt-6 50 ? 60 ? 400 mil 50 pin plastic tsop ii notes 1,2 1 1 v ss supply voltage v 0 0 0 2 t a 70 ambient temperature under bias c - 0 gm71vs65163al GM71V65163A
dc electrical characteristics: (v cc = 3.3v+/-10%, t a = 0 ~ 70c) symbol parameter note v oh v ol output level output level voltage (i out = -2ma) unit v v max v cc 0.4 min 2.4 0 output level output level voltage (i out = 2ma) i cc1 200 - operating current ( t rc = t rc min) 50ns ma 60ns 180 - i cc2 ma standby current (ttl interface) power supply standby current (ras, ucas,lcas= v ih , d out = high-z) 2 - i cc3 ma ras-only refresh current ( t rc = t rc min) i cc4 ma extended data out page mode current (ras = v il , cas, address cycling: t hpc = t hpc min) - 50ns 60ns - 120 - 50ns 60ns 110 - i cc6 ma cas-before-ras refresh current (t rc = t rc min) - 50ns 60ns - i cc8 ma standby current (cmos) power supply standby current ras = v ih ,ucas, lcas = v il , d out = enable 5 - i i(l) 5 -5 i o(l) 5 -5 input leakage current, any input (0v<=v in <=vcc) output leakage current (d out is disabled, 0v<=v out <=vcc) note: 1. i cc depends on output load condition when the device is selected. i cc(max) is specified at the output open condition. 2. address can be changed once or less while ras = v il . 3. measured with one sequential address change per edo cycle, t hpc . 4. v ih >=v cc -0.2v, 0v<=v il <=0.2v 5. l-version 3 lg semicon 200 180 160 140 500 400 battery back up operating current(standby with cbr) (trc=31.25us,,tras=300ns,dout=high-z) self refresh current (ras,ucas,lcas <=0.2v,dout=high-z) i cc7 i cc9 standby current(l_version) ua 300 - ua ma cmos interface (ras, ucas,lcas>=v cc -0.2v, d out = high- z) 0.5 - - - i cc5 1,2 2 1 1,3 4 ua ua ua 4, 5 5 gm71vs65163al GM71V65163A
4 symbol parameter note c i1 c i2 c i/o input capacitance (address) input capacitance (clocks) output capacitance (data-in,data-out) 1 1 1, 2 unit ? ? ? max 5 7 7 typ - - - note: 1. capacitance measured with boonton meter or effective capacitance measuring method. 2. ras, ucas and lcas = v ih to disable d out . capacitance (v cc = 3.3v+/-10%, t a = 25c) lg semicon read, write, read-modify-write and refresh cycles (common parameters) ac characteristics (v cc = 3.3v+/-10%, t a = 0 ~ 70c, notes 1,2,19,20) test conditions input rise and fall times : 2ns output timing reference levels : v ol /v oh = 0.8/2.0v input level : v il /v ih = 0.0/3.0v output load : 1 ttl gate+c l (100pf) input timing reference levels : v il /v ih = 0.8/2.0v (including scope and jig) symbol parameter min gm71v(s)65163a/al-5 max t rc random read or write cycle time t rp ras precharge time t ras ras pulse width t cas cas pulse width t asr row address set-up time t rah row address hold time t asc column address set-up time t cah column address hold time t rcd ras to cas delay time 4 t rad ras to column address delay time 3 t rsh ras hold time t csh cas hold time t crp cas to ras precharge time max min 84 104 40 60 10 0 10 0 10 14 12 17 40 5 30 50 8 0 8 0 8 12 10 13 35 5 - - - 25 37 - - - - 10000 - - - - 10000 - - - - 45 30 - - - unit notes ? ? ? ? ? ? ? ? ? ? ? ? ? t t transitiontime (rise and fall) t ref refresh period 2 - 2 - 64 50 50 64 ? a t odd oe to d in delay time t dzo oe delay time from d in t dzc cas delay time from d in 15 0 0 13 0 0 - - - - - - ? ? ? gm71v(s)65163a/al-6 t cp cas precharge time 10 8 - - ? 22 10000 10000 refresh period ( l-version ) - - 128 128 a 24 21 21 5 6 6 7 4096 cycles 4096 cycles gm71vs65163al GM71V65163A
read cycles 5 lg semicon symbol parameter min gm71v(s)65163a/al-5 gm71v(s)65163a/al-6 max max min - - - - 0 0 0 30 - - 0 0 0 25 - - - 25 13 50 60 15 30 - - - unit notes ? ? ? ? ? ? ? ? - - t rac t cac t aa t rcs t rch t rrh t ral t cal access time from ras access time from cas access time from column address read command set-up time read command hold time to cas read command hold time to ras column address to ras lead time column address to cas lead time 8,9 t oac access time from oe - 13 - 15 ? 15 - 18 - 9,10,17 9,11,17 ? ? t rdd t wdd ras to d in delay time ? t ofr output buffer turn-off delay time from ras ? t wez output buffer turn-off delay time from we 13 13 - - 13 - 15 13 - 15 - 15 - - 15 - 13 ? ? ? t clz t oh t cdd cas to output in low - z output data hold time cas to d in delay time - 15 - ? ? t ohr t oez output data hold time from ras output buffer turn-off delay time from oe ? t off 0 3 - - 13 15 13 - 15 - - - 3 - - - - we to d in delay time 13,26 13 ? t rchr read command hold time from ras 50 - 60 - ? t oho output data hold time from oe 3 - 3 - 0 output buffer turn-off delay time from cas 12,22 9 12 13,26 13 3 3 21 26 5 26 gm71vs65163al GM71V65163A
6 lg semicon write cycles read-modify-write cycles t rwc read-modify-write cycle time t rwd ras to we delay time t cwd cas to we delay time t awd column address to we delay time refresh cycle symbol parameter min max max min 116 140 79 34 49 67 30 42 - - - - - - - - unit notes ? ? ? ? refresh cycles t csr cas set-up time (cas-before-ras refresh cycle) t chr cas hold time (cas-before-ras refresh cycle) t rpc ras precharge to cas hold time symbol parameter min max max min 5 5 - - unit notes ? 8 10 - - 5 5 - - ? ? t oeh oe hold time from we 15 13 - - ? 14 gm71v(s)65163a/al-5 gm71v(s)65163a/al-6 gm71v(s)65163a/al-5 gm71v(s)65163a/al-6 t wcs write command set-up time t wch write command hold time t wp write command pulse width t rwl write command to ras lead time t cwl write command to cas lead time t ds data-in set-up time t dh data-in hold time symbol parameter min max max min 0 0 10 10 10 0 10 8 8 8 0 8 - - - - - - - - - - - - unit notes ? ? ? ? ? ? ? - - 14,21 15,23 15,23 gm71v(s)65163a/al-5 gm71v(s)65163a/al-6 17 13 14 14 t wrp we setup time (cas-before-ras refresh cycle) 0 0 - - ? t wrh we hold time (cas-before-ras refresh cycle) 8 10 - - ? 21 23 21 22 21 gm71vs65163al GM71V65163A
extended data out mode cycles t hpc edo page mode cycle time t wpe write pulse width during cas precharge t rasp edo mode ras pulse width t acp symbol min max max min 20 25 10 - - 8 - - 28 100000 - - - - 35 unit notes ? ? ? ? parameter 7 lg semicon gm71v(s)65163a/al-5 gm71v(s)65163a/al-6 access time from cas precharge - ras hold time from cas precharge t cpw edo page mode read-modify-write cycle cas precharge to we delay time t hprwc 28 35 54 68 45 57 - - - - 100000 - ? ? ? - edo read-modify-write cycle time t rhcp t col cas hold time referred oe t cop 10 5 8 5 - - - - ? ? cas to oe set-up time read command hold time from cas precharge t doh output data hold time from cas low 28 35 - - ? ? t rchp 3 3 - - 25 9,17,22 self refresh cycles (l_version) t rass ras pulse width(self-refresh) t rps symbol parameter min max max min 100 - - unit notes us gm71v(s)65163a/al-5 gm71v(s)65163a/al-6 t chs 100 ras prechartge time(self-refresh) 90 - - 110 cas hold time(self-refresh) -50 - - -50 31 31 23 16 9,27 14,22 t oep oe precharge time ? 10 8 - - symbol min max max min unit notes parameter gm71v(s)65163a/al-5 gm71v(s)65163a/al-6 edo page mode read-modify-write cycle us us gm71vs65163al GM71V65163A
8 lg semicon notes: ac measurements assume t t = 2 ? . ac initial pause of 200us is required after power up followed by a minimum of eight initialization cycles ( any combination of cycles containing ras-only refresh or cas-before- ras refresh) operation with the t rcd (max) limit insures that t rac (max) can be met, t rcd (max) is specified as a reference point only: if t rcd is greater than the specified t rcd (max) limit, then access time is controlled exclusively by t cac . operation with the t rad (max) limit insures that t rac (max) can be met, t rad (max) is specified as a reference point only: if t rad is greater than the specified t rad (max) limit, then access time is controlled exclusively by t aa . either t odd or t cdd must be satisfied. either t dzo or t dzc must be satisfied. v ih (min) and v il (max) are reference levels for measuring timing of input signals. also, transition times are measured between v ih (min) and v il (max). assumes that t rcd <=t rcd (max) and t rad <=t rad (max). if t rcd or t rad is greater than the maximum recommended value shown in this table, t rac exceeds the value shown. measured with a load circuit equivalent to 1 ttl loads and 100 pf. assumes that t rcd >=t rcd (max) and t rcd + t cac (max) >=t rad + t aa (max). assumes that t rad >=t rad (max) and t rcd + t cac (max)<=t rad + t aa (max). either t rch or t rrh must be satisfied for a read cycles. t off (max), t oez( max), t ofr (max) and t wez (max) define the time at which the outputs achieve the open circuit condition and is not referenced to output voltage levels. t wcs , t rwd , t cwd, t awd, and t cpw are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only: if t wcs >=t wcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle: if t rwd >=t rwd (min), t cwd >=t cwd (min), t awd >=t awd (min) and t cpw >=t cpw (min), the cycle is a read- modify-write and the data output will contain data read from the selected cell: if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. t ds and t dh are referred to ucas and lcas leading edge in early write cycles and to we leading edge in delayed write or read-modify-write cycles. t rasp defines ras pulse width in extended data out mode cycles. access time is determined by the longest among t aa, t cac and t acp . in delayed write or read-modify-write cycles, oe must disable output buffer prior to applying data to the device. when output buffers are enabled once, sustain the low impedance state until valid data is obtained. when output buffer is turned on and off within a very short time, generally it causes large v cc /v ss line noise, which causes to degrade v ih min/v il max level. when both ucas and lcas go low at the same time, all 16-bit data are written into the device. ucas and lcas cannot be staggered within the same write/read cycles. t asc, t cah, t rcs, t wcs, t wch, t csr and t rpc are determined by the earlier falling edge of ucas or lcas. t crp, t chr, t rch, t acp and t cpw are determined by the later rising edge of ucas or lcas. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. gm71vs65163al GM71V65163A
9 lg semicon t cwl, t dh, t ds and t chs should be satisfied by the both ucas and lcas. t cp is determined by the time that both ucas and lcas are high. t hpc (min) can be achieved during a series of edo mode early write cycles or edo mode read cycles. if both write and read operation are mixed in a edo mode, ras cycle { edo mode mix cycle (1),(2) } minimum value of cas cycle t hpc (t cas + t cp + 2t t ) becomes greater than the specified t hpc (min) value. the value of cas cycle time of mixed edo page mode is shown in edo page mode mix cycle (1) and (2). data output turns off and becomes high impedance from later rising edge of ras and cas. hold time and turn off time are specified by the timing specifications of later rising edge of ras and cas between t ohr and t oh , and between t ofr and t off . t doh defines the time at which the output level go cross. v ol =0.8v, v oh =2.0v of output timing reference level. before and after self refresh mode, execute cbr refresh to all refresh addresses in or within 64 a period on the condition a and b below. a. enter self refresh mode within 15.6us after either burst refresh or distributed refresh at equal interval to all refresh addresses are completed. b. start burst refresh or distributed refresh at equal interval to all refresh addressed within 15.6us after exiting from self refresh mode. in case of entering from ras-only-refresh, it is necessary to execute cbr refresh before and after self refresh mode according as note 28. for l_version, it is available to apply each 128 a and 31.2us instead of 64 a and 15.6us at note 28. at t rass ? 100 us , self refresh mode is activated, and not active at t rass ? 10us. it is undefined within the range of 10 us ? t rass ? 100 us . for t rass ? 10 us , it is necessary to satisfy t rps . xxx: h or l ( h : v ih (min)<=v in <=v ih (max), l: v ih (min)<=v in <=v ih (max)) ///////: invalid dout when the address, clock and input pins are not described on timing waveforms, their pins must be applied v ih or v il. 23. 24. 25. 26. 27. 28. 29. 30. 31. 32. gm71vs65163al GM71V65163A
10 lg semicon timing waveforms figure 1. read cycle* 32 t rc t ras t rp ras t csh t crp t rcd t rsh t cas t t t rad t ral t asr t rah address row column t rcs t rch t rrh we t asc t cah d out d out d in t dzc t cdd high-z t odd oe t dzo t oac t cac t aa high-z t rac t oez t off t cal t rchr t wdd ucas lcas t clz t oho t oh t ofr t ohr t wez t rdd gm71vs65163al GM71V65163A
11 lg semicon figure 2. early write cycle t wcs t wch we d out d in t ds t dh high-z t rc t ras t rp ras t csh t crp t rcd t rsh t cas t t t asr t rah t asc t cah address column row * t wcs t wcs (min) > = d in ucas lcas gm71vs65163al GM71V65163A
12 lg semicon figure 3. delayed write cycle* 18 t rc t ras t rp ras t csh t crp t rcd t rsh t cas t t t asr t rah t asc t cah address column t rcs we d out row d in t wp t rwl t cwl t odd t oeh invalid output d in oe t dzc t dh t ds high-z t dzo t oez high-z ucas lcas t clz t oep gm71vs65163al GM71V65163A
13 lg semicon figure 4. read modify write cycle* 18 t rwc t ras t rp ras t crp t rcd t t t asr t rah t asc t cah address column we row d in t wp t rwl t cwl t odd t oeh d in t dzc t dh t ds high-z t rad t cwd t awd t rwd t rcs t dzo d out t oac oe t oez t cac t aa t rac t cas high-z ucas lcas d out t clz t oho t oep gm71vs65163al GM71V65163A
14 lg semicon figure 5. ras only refresh cycle ras address row t asr t rah t crp t rpc t rp t ras t rc t t figure 6. cas before ras refresh cycle t crp ucas lcas ras t rp t t cas d out high-z t off t ras t rp t ras t rp t rc t rc t cp t rpc t csr t chr t cp t rpc t csr t chr t crp address we t wrp t wrh t wrp t wrh t ofr d out high-z t off t ofr gm71vs65163al GM71V65163A
15 lg semicon figure 7. hidden refresh cycle ras t ras t t t rc t rc address we t rp t ras t rp t ras t rp t rc t rcd t rsh t chr t crp t rad t ral column row t asr t rah t asc t cah t rcs d in high-z t cas t rrh t rch t dzc t wdd t ohr oe t dzo t oac t odd d out d out ucas lcas t ofr t oez t wez t oho t oh t off t clz t rac t aa t cac t cdd t rdd gm71vs65163al GM71V65163A
16 lg semicon figure 8. extended data out page mode read cycle ras address we t rasp t rp row column column column oe t t d out d out 1 d out 2 high-z ucas lcas d in high-z column d out 2 d out 3 d out 4 t hpc t crp t hpc t rchr t cp t cp t cp t rhcp t csh t cas t cas t cas t cas t rsh t rcs t rch t wpe t rrh t rch t rchp t asr t rah t asc t cah t asc t cah t asc t cah t asc t cah t ral t wdd t dzc t cal t cal t cal t cal t cdd t rdd t odd t oep t col t oep t cop t dzo t rac t aa t cac t oac t acp t wez t aa t cac t oez t oho t acp t aa t cac t oac t doh t oez t oho t acp t aa t cac t oac t ohr t ofr t oez t oho t off t oh gm71vs65163al GM71V65163A
17 lg semicon figure 9. extended data out mode read cycle (2cas control) ras address we t rasp t rp row column column column oe t t ld out d out 1 d in high-z column d out 2 d out 4 t crp t hpc t rch t asr t rah t asc t cah t asc t cah t asc t cah t asc t cah t ral t wdd t dzc t cal t cal t cal t cal t cdd t rdd t odd t oep t col t oep t cop t dzo t rac t aa t cac t oac d out 1 d out 3 d out 2 t hpc t hpc t csh t cas t cas t cas t cas t cp t cp t cp t rsh t rcs t rrh t rchp lcas ucas t doh t acp t aa t cac t oho t oez t oac t cac t acp t aa t oho t oez d out 4 t oac t acp t aa t cac t ofr t ohr t oez t oho t off t oh ud out gm71vs65163al GM71V65163A
18 lg semicon figure 10. extended data out mode early write cycle *t wcs >=t wcs (min) ras d in address we t t column 1 row column 2 column n t rcd t cas t csh t cp t cas t hpc t cp t cas t asr t rah t rasp t rp d in 1 d in 2 d in n d out high-z* t rsh t crp t asc t cah t asc t cah t asc t cah t wcs t wch t wcs t wch t wcs t wch t ds t dh t ds t dh t ds t dh ucas lcas gm71vs65163al GM71V65163A
19 lg semicon figure 11. extended data out mode delayed write cycle* 18 ras d in address we row d out invalid d out oe column 1 d in 1 column 2 column n t rasp t rp t t t rcd t cas t csh t cp t cas t hpc t cp t cas t rsh t crp t asr t rad t rah t asc t cah t asc t cah t rcs t rcs t cwl t cwl t rcs t cwl t rwl t dzc t wp t ds t dh t dzc t wp t ds t dh t dzc t wp t ds t dh t asc t cah t dzo t odd t oeh t dzo d in 2 t odd t dzo t oeh d in n t odd t oeh t clz t oez invalid d out t clz t oez invalid d out t oez t clz high-z ucas lcas t oep t oep gm71vs65163al GM71V65163A
20 lg semicon figure 12. extended data out mode read modify write cycle* 18 ras d in address we row d out oe column 1 d in 1 column 2 column n t rasp t rp t t t rcd t cas t cp t cas t hprwc t cp t cas t rsh t crp t asr t rad t rah t asc t cah t asc t cah t rcs t rcs t cwl t cwl t rcs t cwl t rwl t dzc t wp t ds t dh t dzc t wp t ds t dh t wp t ds t dh t asc t cah t odd t oeh d in 2 t odd t oeh d in n t odd t oeh t rwd t awd t cwd t cpw t awd t cwd t cpw t awd t cwd t dzc t dzo t dzo t oho t oac t cac t aa t rac t clz t oez d out 1 d out 2 d out n high-z t oho t oac t cac t acp t clz t oez t aa t oho t oac t acp t clz t oez t aa t cac t dzo high-z ucas lcas t oep t oep t oep gm71vs65163al GM71V65163A
21 lg semicon figure 13. extended data out mode mix cycle (1)* 25 ras t rasp t rp t t t cp t cp t cas t cas t cp t cas t crp t rcd t csh t cas address row column 1 column 2 column 3 column 4 oe d in 1 d in 3 dout d out 2 d out 4 t rah t asr t cah t cah t cah t cah high - z t rdd t cdd t ds t dh t odd t doh t cac t cac t cac t wez din t asc t asc t asc t asc t wcs t wch t ds t dh t wdd t aa t oac t acp t acp t aa t oez t oez t aa t oac t acp t oh d out 3 t off t ofr t cpw t awd t wp t rsh t rrh t rch t ral we high - z ucas lcas t rcs t cal t cal t oep t oho gm71vs65163al GM71V65163A
22 lg semicon figure 14. extended data out mode mix cycle (2)* 25 ras t rasp t rp t t we address row column 1 column 2 column 3 column 4 oe d in 2 d in 3 dout d out 1 d out 4 t csh t cp t cp t cas t cas t cp t cas t crp t rcd t rchr t cas t rcs t rch t wcs t wch t wp t rsh t rrh t rch t rah t asr t asc t cah t asc t asc t cah t cah t cpw t ral t asc t cah high - z t cal t cal t cal t cal t rdd t cdd t ds t dh t ds t dh t odd t col t odd t cop t aa t cac t oac t acp t cac t oac t acp t aa t oez t oez t cac t aa t oac t rac t wez t oez t off t oh t ofr din d out 3 high - z ucas lcas t oho t oep t oep t wdd t oho gm71vs65163al GM71V65163A
lg semicon 23 figure 15. self refresh cycle* 28,29,30,31 ras lcas dout t rass t rps high-z t csr t chs we t rp t crp t rpc t cp t off t ofr t wrp t wrh t t ucas gm71vs65163al GM71V65163A
24 lg semicon tsop 50 pin package dimension unit: mm 10.16 21.35 max 20.95 min 0.30 0.10 0.80 0.18 max 0.08 min 0.60 max 0.40 min 0.125 0.04 0 ~ 5 ? 0.145 0.05 1.15 max 0.28 0.08 1.20 max 0.10 11.96 max 11.56 min 0.80 0.68 dimension including the plating thickness base material dimension soj 50 pin package dimension gm71vs65163al GM71V65163A

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